The Timing Analyzer is an ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format. This page provides links to resources where you can learn more about the Timing Analyzer.
For resources on the Timing Analyzer, see the following:
For a brief overview of the Timing Analyzer, refer to the Timing Analyzer section on the Verification and Board Level product feature page.
To search for known Timing Analyzer issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect to and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Timing Analyzer Resources
Table 1. Timing Analyzer Documentation
|AN775: I/O Timing Information Generation Guidelines||
This Application Note demonstrates techniques to generate I/O timing information for any given device using the Quartus Prime software.
|Timing Analyzer (PDF)||This chapter of the Quartus® II Development Software Handbook describes features of the Timing Analyzer and how to constrain your design with SDC commands.|
|Applying Multicycle Exceptions in the Timing Analyzer (PDF)||This application note details how to apply multicycle exceptions in the Timing Analyzer.|
|Quartus Prime Timing Analyzer Cookbook (PDF)||This cookbook provides various design examples and templates showing how to apply timing constraints to various design circuits.|
|Switching to the Timing Analyzer (PDF)||This chapter of the Quartus II Development Software Handbook describes how to switch a design from the classic analyzer to the Timing Analyzer.|
|Timing Analyzer Quick Start Tutorial (PDF)||This tutorial provides a quick introduction to the Timing Analyzer.|
|SDC and Timing Analyzer API Reference Manual (PDF)||This reference manual provides a list of all SDC commands supported by the Timing Analyzer, as well as the complete Tool Command Language (Tcl) API.|
|AN 471: High-Performance FPGA PLL Analysis with Timing Analyzer (PDF)||This application note describes how to analyze and constrain phase-locked loops (PLLs) using the Timing Analyzer.|
|Performing Equivalent Timing Analysis Between Altera Timing Analyzer and Xilinx Trace white paper (PDF)||This white paper shows how to perform equivalent static timing analysis between Altera's Timing Analyzer and Xilinx's Trace.|
|Timing Analyzer Clock Analyzer||Provides detailed information about clock analysis, including derivation of equations for timing analysis.|
|Timing Analyzer Exceptions||Gives an overview of Timing Analyzer SDC exceptions and their precedence.|
|Timing Analyzer Collections||Lists all the supported collections (a core part of the Timing Analyzer).|
|Timing Analyzer GUI||Familiarizes you with the Timing Analyzer GUI and its features.|
Table 2. Timing Analyzer Training and Demonstrations
Timing Analyzer (English)
|You will use the Timing Analyzer static timing analyzer tool in the Quartus II software to verify performance of an FPGA or HardCopy® ASIC. You will also create timing constraints (i.e., assignments) using the Timing Analyzer analyzer. You will use supported SDCs and generate timing reports from the Timing Analyzer analyzer's user interface and from script files.
This is a 1.5-hour online course.
|Constraining Source-Synchronous Interfaces
|This training shows you how to constrain and analyze single data rate source-synchronous interfaces with the Timing Analyzer timing analyzer in the Quartus II software. You will learn the benefits of source-synchronous interfaces as compared to common clock system interfaces. You will be able to write SDC constraints to constrain single data-rate, source-synchronous inputs and outputs. You will also learn to use the Timing Analyzer timing analyzer to report and analyze timing for source-synchronous outputs and inputs.
This is a 1-hour online course.
|Constraining Double Data Rate Source Synchronous Interfaces
|This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock constraints, data constraints, and timing exceptions for both input and output DDR interfaces. Finally, you’ll learn how to analyze DDR source synchronous interface timing with the Timing Analyzer timing analyzer.
This is a 30-minute online course.
|The Quartus II Software Design Series: Foundation
|You will learn how to use the Quartus II software to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, compile to your target FPGA or CPLD, and configure your device using the Quartus II programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the Timing Analyzer, the timing analyzer in the Quartus II software.
This is an 8-hour instructor-led course.
|The Quartus II Software Design Series: Timing Analysis
|You will learn advanced features of the Quartus II software that will enable you to verify your FPGA design. You will learn how to constrain and analyze a design for timing, including understanding FPGA timing parameters, writing SDC files, generating various timing reports in the Timing Analyzer timing analyzer, and applying this knowledge to an FPGA design. You will also estimate FPGA power consumption using Quartus II software tools and EDA simulation tools.
This is an 8-hour instructor-led course.