Verilog HDL: Dual Clock Synchronous RAM

This example describes a 64-bit x 8-bit dual clock synchronous RAM design with different read and write addresses in Verilog HDL. Synthesis tools are able to detect dual clock synchronous RAM designs in the HDL code and automatically infer either the altsyncram or altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Dual Clock Synchronous RAM Top-Level Diagram

Figure 1. Dual Clock Synchronous RAM Top-Level Diagram

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Table 1 lists the ports in the dual clock synchronous RAM design.

Table 1. Dual Clock Synchronous RAM Port Listing

Port NameTypeDescription
data[7:0]Input8-bit data input
read_addr[5:0]Input6-bit read address input
write_addr[5:0]Input6-bit write address input
weInputWrite enable input
read_clockInputRead clock input
write_clockInputWrite clock input
q[7:0]Output8-bit data output

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