Verilog: Coefficients Reload Design Example for FIR Compiler

This design example demonstrates how to reload coefficients from a file when using the Altera® finite impulse response (FIR) Compiler IP MegaCore®function. FIR Compiler provides the flexibility to change the coefficients at run time. While the FIR Compiler is processing the data with one set of coefficients, you can reload another set without halting core processing.

To optimize silicon efficiency, coefficients are not stored in their natural order. This example explains the steps for reordering the coefficients using the precompiled executable coef_seq.exe. The filter uses four sets of coefficients: low pass, high pass, band pass, and band reject filters. The first two are parameterized in the IP Toolbench; the latter two must be reloaded at run time and require reordering in advance. The provided testbench shows you how to set up controls to reload the coefficients to meet the timing requirements.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Files in the zip download include:

  • fir91.v - FIR compiler wrapper file
  • coef_reload_tb.v - Testbench file
  • coef_reload_msim.tcl - Tcl script for running a functional simulation using the ModelSim® tool
  • coef_seq.exe - Windows executable that reorders the coefficients

Figure 1. FIR Compiler Port Listing

Table 1 lists the FIR compiler ports and gives a description for each.

Table 1. FIR Compiler Port Listing

Port Name Type Description
clkInputClock signal
reset_nInputSynchronous active low reset signal
sink_data[15:0]InputSample input data
coef_setInputSelect which coefficient set used for the calculation
sink_validInputAsserted when input data is valid
source_readyInputAsserted by the downstream module if it is able to accept data
sink_error[1:0]InputError signal indicating Avalon®-ST protocol violations on the sink side
coef_set_inInputSelects which coefficient set to be reloaded
coef_weInputActive high write-enable signal
coef_in[18:0]InputInput coefficient value when reloading coefficient
source_data[37:0]OutputFilter output
sink_readyOutputAsserted by the FIR filter when it is able to accept data
source_validOutputAsserted by the FIR filter when there is valid data to output
source_error[1:0]OutputError signal indicating Avalon-ST protocol violations on the source side

Table 2 shows the FIR compiler parameters.

Table 2. FIR Compiler Parameters

FIR Parameters Values
Filter RateSingle
# of Input Channels1
Input Bitwidth16
Output Bitwidth38 (Full Resolution)
Coefficient Bitwidth


# of Coefficient Set


# of Coefficient in Each Set


Device FamilyStratix® IV
StructureDA: Fully Parallel Filter
Pipeline Level1
Data StorageLogic Cells
Coefficient StorageM512
Coefficient Reload BoxChecked
Use Single Clock BoxChecked

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