POS-PHY LEVEL 4 (SPI4.2) Loopback Design Example on Stratix III/IV Development Board

Design Summary

This design implements the POS-PHY LEVEL 4 (SPI4.2) MegaCore® function instance with user logic on the Stratix III/IV development board. The design performs a loopback test, transporting packets from the SPI4.2 Tx instance to the SPI4.2 Rx instance. Loopback functionality is achieved by using an HSMC daughtercard in HSMC port A of the development board to loop back the packet from Tx to Rx, as shown in Figure 1. This test demonstrates the robustness of the core logic by transmitting a large number of packets with no error at the receiver.

Download the files used in the examples:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Files in the download include:

  • top.qar - Archive of SPI4.2 Design example

Figure 1. Conceptual SPI-4.2 Loopback Block Diagram

Figure 1. Conceptual SPI-4.2 Loop Back Block Diagram

Simulating the Design

  1. Open the archive and recompile the module ‘top’ with the appropriate speed grade setting for your device.
  2. Open the files stp1.stp and Spf1.spf.
  3. After power on, program the top.sof file onto the Stratix III/IV development board.
  4. Reset by toggling the reset_n signal of Spf1.spf.

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