This example describes a 64-bit x 8-bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in Verilog HDL. The design unit dynamically switches between read and write operations with the write enable input of the respective port. Synthesis tools are able to detect RAM designs in the HDL code and automatically infer the altsyncram or altdpram megafunctions depending on the target device architecture.

Figure 1. True Dual-Port RAM with a Single Clock Top-Level Diagram

Figure 1. True Dual-Port RAM with a Single Clock Top-Level Diagram

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Table 1 lists the ports of the true dual-port RAM with a single clock design.

Table 1. True Dual-Port RAM with a Single Clock Port Listing

Port NameTypeDescription
dataa[7:0], datab[7:0]Input8-bit data inputs of port A and port B
addr_a[5:0], addr_b[5:0]Input6-bit address inputs of port A and port B
we_a, we_bInputWrite enable inputs of port A and port B
clkInputClock input
q_a[7:0], q_b[7:0]Output

8-bit data outputs of port A and port B

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