This example describes a 64-bit x 8-bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in Verilog HDL. The design unit dynamically switches between read and write operations with the write enable input of the respective port. Synthesis tools are able to detect RAM designs in the HDL code and automatically infer the
altdpram megafunctions depending on the target device architecture.
Figure 1. True Dual-Port RAM with a Single Clock Top-Level Diagram