This simple example shows how to instantiate a tri-state buffer in Verilog HDL using the keyword bufif1. The output type is tri. The buffer is instantiated by bufif1 with the variable name b1.

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tristate.v

module Tristate (in, oe, out);

    input   in, oe;
    output  out;
    tri     out;

    bufif1  b1(out, in, oe);

endmodule

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