The CIC Decimation Filter with Multichannel Data Support design example demonstrates how to use Altera's Cascaded Integrator-Comb (CIC) Filter MegaCore® function to implement digital sample rate down conversion for multiple independent data sources.
Digital signal processing (DSP) systems often need to work with multiple parallel channels. For digital data rate downconversion or up conversion applications (if different channels have identical rate change requirements), instead of duplicating the same hardware for each input channel, time sharing of low rate hardware sections can provide significant resource reuse. This is the concept of multichannel operation of the Altera® CIC Filter MegaCore function.
In this example, we configure the CIC compiler to support multiple interfaces so we can take advantage of resource saving in the multiple-input-single-output (MISO) mode for decimation. The overall system diagram is shown in Figure 1. For more information on CIC multichannel support, refer to the CIC Compiler User Guide (PDF).
This demonstration has the following features:
- The CIC filter is configured to have two independent interfaces to support parallel input data channels. This allows the CIC filter to time share the low data comb filter sections for all input channels.
- Altera's finite impulse response (FIR) compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop.
- The FIR compiler uses the multi-cycle-variable (MCV) architecture, which reuses multipliers and provides additional resource saving. For more information on MCV architecture, refer to the FIR Compiler User Guide (PDF).
- A MATLAB script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass band ripple and stop band attenuation.
- Altera's Avalon® Streaming Interface is used to transfer packet data from multiple data sources between MegaCore functions. For more information about the Avalon Stream Interface, refer to the Avalon Streaming Interface specification.
- The Avalon Streaming Packet Format Converter is included to properly interleave/de-interleave multiple data channels.
Figure 1 shows the flow of the DSP builder design for the down conversion example. The inputs to the design example are two independent data sources. One source signal is a sine wave and the other is a cosine wave. Both have a frequency of 2.5 MHz. Part of the input signal is corrupted by high-frequency additive noise. The data sources generate continuous data; therefore the startofpacket and endofpacket signals of the Avalon Streaming interface are configured to indicate streaming data.
In this example, two parallel input data sources generate streaming data sampled at 80 MHz with 100 percent bus utilization. The CIC filter implements the bulk of rate change, in this case down sampling by 4. It is configured to have the MISO structure, where parallel input channels time share the comb filter sections as they exit the CIC filter. CIC filter outputs interleaved multi-channel data, where startofpacket and endofpacket signals indicate the corresponding channel boundary. Therefore, the CIC output bus utilization is 50 percent. A FIR filter follows the CIC filter to provide compensation to CIC filter frequency droop and additional decimation by 2. Its output bus utilization becomes 25 percent. The packet format converter de-interleaves the low rate data and generates two source ports for data display. Each data channel output one valid sample every 8 clock cycles.
If the narrowband source signals have a bandwidth that is smaller than the cutoff frequency of the cascaded rate change filters, well defined decimation systems should preserve the input signal bandwidth. In this example, the source signals are sinusoidal signals with a carrier frequency of 2.5 MHz, which is smaller than the designed cutoff frequency 4 MHz. As expected, the output signal spectrum has a spike at 2.5 MHz and the high-frequency noise is filtered out.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Tables 1 and 2 list the parameter settings used in the interpolation example.
Table 1. Parameters for CIC Compiler
|Number of Stages||4|
|Rate Change Factor||4|
|Number of Interfaces||2|
|Number of Channels Per Interface||1|
|Input Data Width||8|
|Output Data Width||16|
Table 2. Parameters for FIR Compiler
|Rate Specification||Decimation by 2|
|Input Bitwidth||Signed Binary 16|
|Output Bitwidth||Full resolution|
|Device Family||Stratix® II|
|Clocks per Output Data||2|
|Coefficients Input||From File|
For more information on features related to those used in this design example, visit:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.