The finite impulse response (FIR) filter is a common algorithm used in digital signal processing (DSP) systems. In this example, a FIR filter has been integrated into a single SOPC Builder component containing Avalon® Memory-Mapped (Avalon-MM) read and write masters. The read master is responsible for supplying the filter with input data, while the write master is responsible for writing the filter response back to memory. Since the filter has Avalon mastering capabilities, you do not need to use a separate direct memory access (DMA) engine to accomplish the filter operation.
When a filter is implemented in software, it requires many clock cycles to complete the calculation of a single output. Using an FPGA, all of these operations can occur concurrently with up to one output calculated every clock cycle. You can implement computationally complex algorithms in hardware to:
- Increase the overall system performance
- Offload the Nios® II embedded processor so that it can perform other tasks
- Decrease the overall design frequency to reduce power consumption
To compile the software, you must have the Nios II Embedded Design Suite (EDS) installed. You can download it for free.
Although this design performs filter operations, you can also reuse the accelerator for your own data transforms. Simply remove the transform block containing the FIR filter and replace it with your own custom logic. You can also reuse the DMA control software. For more information about replacing the FIR filter, refer to the transform.v file supplied with the example design.
Hardware Design Specifications
- Nios Development Board, Cyclone® II or Stratix® II FPGA Edition
- Nios II core: Nios II/f debug-enabled, 4 KB I-cache, 2 KB D-cache
- SSRAM: 2 MB
- DDR SDRAM: 32 MB
- Timestamp timer: 10 us resolution
- JTAG UART
- Phase-locked loop (PLL)
- System ID
- Custom FIR hardware accelerator with Avalon-MM masters
- Also supports Embedded Systems Development Kit, Cyclone III Edition (3C120) and Nios II Embedded Evaluation Kit, Cyclone III Edition (3C25)
Hardware Acceleration Results
In this example (Figure 1), the hardware accelerator is capable of operating over 500 times faster than the equivalent FIR algorithm compiled for the Nios II processor.
Figure 1. Accelerated FIR with Built-In DMA Block Diagram
Using This Design Example
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building the design.
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