Avalon Memory-Mapped Slave Template

The template provided contains an Avalon® Memory-Mapped (MM) Verilog module bundled as an SOPC Builder-ready component. The component is parameterizable, allowing you to select functionality on a per-register basis. You can use the component with any Altera® device family supported by SOPC Builder. The component is Verilog based, so you can add your own functionality or simply use it as a reference. For ease of use, the component uses Tcl callbacks to allow you to make setting changes automatically in a GUI environment.

You can use this component as a replacement for the PIO component that is available from SOPC Builder. This component implements the same logic, but it is duplicated for up to 16 I/O pairs. This component also supports data widths ranging from 8 to 1,024 bits with an optional loopback mode to allow software developers to readback the output contents. Version 2.0 of this component supports input ports (or read register files) with interrupt capabilities for data widths ranging from 8 to 32 bits. Interrupts are generated by the rising edge data toggle at the input ports.

Figure 1. Component Block Diagram

Figure 1.  Component Block Diagram
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Each I/O pair is capable of the access types shown in Table 1.

Table 1. Component Modes

Mode Description
Output OnlyOutput register exposed at top level, input is disabled
Input OnlyInput register exposed at top level, output is disabled
Output and InputOutput and input registers exposed at top level
Output with LoopbackOutput register exposed at top level, output register supports reads, input is disabled
DisabledOutput and input is disabled

The component also optionally provides synchronization signals that you can use to determine when an Avalon-MM master accesses one of the registers. For example, your own custom logic connected to one of the output data ports can use the synchronization signals to signify that the data is valid. Another example is one of the inputs could be connected to a FIFO buffer. The user_chipselect and user_read signals could be used as the read acknowledge signal for the FIFO buffer.

Using This Design Example

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

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