Nios II Ethernet Acceleration Design Example

This design example demonstrates how to achieve high levels of networking performance using the Nios® II processor, the NicheStack Networking Stack Nios II Edition, and the Altera® Triple Speed Ethernet MAC design example.

This example also uses the Triple Speed Ethernet-SGDMA design example for the Stratix® IV GX FPGA Development Kit (230 Edition). The Triple Speed Ethernet-SGDMA design example for the Triple Speed Ethernet MAC design example uses the Scatter Gather DMA (SGDMA) peripherals to transfer data. However, to increase overall networking performance, several optimizations have been applied to the system design.

A simple network benchmark program is also included as a part of this example to measure the effective throughput of TCP and UDP data transfers. Additionally, you can use this benchmark program to measure how various hardware and software optimizations impact the total networking performance of the system.

Required Hardware and Software

  • Quartus® Prime or Quartus II software, version 12.1 (or later)
  • Nios II Embedded Design Suite (EDS) version 12.1 (or later)
  • Stratix IV GX FPGA Development Kit (230 Edition)

Hardware Design Specifications

The hardware design used in this example targets the Stratix IV GX FPGA Development Kit. Key peripherals in this design include the following:

  • Nios II processor core (Nios II/f core with instruction and data cache)
  • Altera Triple Speed Ethernet MAC 10/100/1000 Mb
  • SGDMA for sending and receiving data
  • SDRAM memory
  • On-chip memory (for packet storage)

Software Design Specifications

C source files are included for the benchmark program and compilation for the Nios II processor or Windows workstation. The benchmark program also uses the Nios II Hardware Abstraction Layer (HAL) and NicheStack Networking Stack, Nios II Edition for its operation.

Download this Design Example

Download the AN440_ethernet_acceleration_example_design.zip.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

The .zip file contains all the necessary software files to reproduce the example for the Stratix IV GX FPGA Development Kit, as well as a readme.doc file. The readme.doc file contains instructions for rebuilding the example.

Download the Application Note

This example was created using the recommendations found in the Altera application note AN 440: Accelerating Nios II Networking Applications. This application note provides a detailed analysis of how to increase the performance of your Nios II processor networking application and includes benchmark results for various systems.

Download Accelerating Nios II Networking Applications.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.