Nios II Low-Power Design Example

This low-power design example demonstrates how to use the Nios® II C-to-Hardware (C2H) acceleration compiler to help reduce dynamic power consumption in an FPGA-based embedded design. The example computes the Mandelbrot fractal pattern using different numbers of hardware accelerators to measure the effects on power consumption and total system throughput.

The design example runs on the economical Cyclone® III FPGA Starter Kit.

The example includes three separate designs. Each represents a different level of hardware acceleration:

  • No hardware accelerator
  • One hardware accelerator
  • Five hardware accelerators

All three of the examples sequentially alter the clock frequency of both the processor and the accelerators so that power can be measured and compared for each configuration.

This example shows that by adding hardware accelerators to a design, you can significantly reduce the clock frequency of the system. This reduces the dynamic power consumption, yet maintains the required level of performance. Table 1 shows the dynamic power measured for three sample configurations.

Table 1. Measured Dynamic Power

System Configuration Nios II
No Accelerator
Nios II
+ 1 Accelerator
Nios II
+ 5 Accelerators
Clock Frequency

80 MHz

40 MHz

20 MHz

Total Dynamic Power (1)

132 mW

72 mW

84 mW

Mandelbrot Calculation Performance

.184 Fps (2)

8.2 Fps

20.1Fps

System Efficiency717 mWs per Frame (3)8.7 mWs per Frame4.1 mWs per Frame

Notes:

  1. Dynamic power is defined as the total power subtract the static power (power measured with no clock applied)
  2. Fps = Frames per second
  3. mWs = Miliwatt seconds

In the five-accelerator system, each accelerator runs autonomously, processing one horizontal line at a time. When it finishes processing a line of the image, it acquires the next available line, and begins processing it. A hardware mutex is used to prevent multiple accelerators from acquiring the same line. Figure 1 shows a block diagram of the five-accelerator system.

Figure 1. Simplified Block Diagram of Five-Accelerator System

Simplified Block Diagram of Five-Accelerator System

Run the Example

To download and run the Nios II Low-Power Design Example, perform the following steps:

  1. Download the .zip file containing the Nios II low-power design example.
  2. Extract the downloaded .zip file to a working directory on your computer.
  3. Connect power and USB cables to your Cyclone III Starter Kit, and connect the other end of the USB cable to one of your computers’ USB connectors. Turn on the power to the board.
  4. Open a Nios II Command Shell and change to the directory where you extracted the .zip file.
  5. Change to the directory "c3_power_c2h_0_accel/software_examples/app/accel_0_test"
  6. Type the command “./create_this_app” to create and build the software project.
  7. Type the command “nios2-configure-sof ../../../c3_power_proj.sof “ to configure the 65-nm FPGA on the Cyclone III Starter Kit board.
  8. Type the command “nios2-terminal” to open a terminal session.
  9. Type the command “make download-elf” to download and run the software on the Nios II processor.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

This will run the Nios II only (no accelerator) design. To run the Nios II plus one accelerator and Nios II plus five accelerators designs, repeat steps 5-9, replacing the path in step 5 with, "c3_power_c2h_1_accel" and "c3_power_c2h_5_accel" respectively.

The board will now print its clock frequency information and Mandelbrot performance measurements to the terminal session. You can measure the total power consumption of the FPGA core by measuring the voltage across a current sensing resistor on the board.

Refer to the Cyclone III FPGA Starter Kit User Guide for full instructions on accurately measuring and calculating FPGA core power consumption.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.