Memory Protection Unit (MPU)

This design example shows the basic features of the Nios® II processor optional memory protection unit (MPU), including how to use the MPU without the support of an operating system (OS).

Hardware Design Specifications

The hardware design used in this example targets the Nios II Embedded Evaluation Kit (NEEK), Cyclone® III Edition. Key peripherals in this design includes :

Nios II/f CPU core with the MPU enabled
On-chip RAM
JTAG UART

Using This Design Example

For information on how to run the design example, please refer to Nios II MPU Usage.
Download the files used in this example: an540_91.zip.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.