Profiling Nios II Systems Design Example

The Profiling Nios® II Systems design example shows different ways to measure the performance of a Nios II system by using the GNU Profiler, the timestamp interval timer component and the performance counter component. The GNU Profiler can be used to identify the areas of code that consume the most processor time. The interval timer and performance counter components can be used to analyze functional bottlenecks in the system.

This design is provided for the following Altera® development kits:

  • Nios II Embedded Evaluation Kit, Cyclone® III Edition
  • Embedded Systems Development Kit, Cyclone III Edition
  • Stratix® IV GX FPGA Development Kit

Using This Design Example

To run this example, download the Nios II Ethernet Standard Design Example and profiler_software_examples.zip. Next, follow the instructions in AN391: Profiling Nios II Systems.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

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Design Examples Disclaimer

These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.