This design example shows the use of tightly coupled memory in designs that include Nios® II processor. By enabling the processor’s tightly-coupled memory master, Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance critical applications. This design is provided for the following Altera® development kits:
- Nios II Embedded Evaluation Kit, Cyclone® III Edition
- Embedded Systems Development Kit, Cyclone III Edition
Stratix® IV GX FPGA Development Kit
Using This Design Example
- Using Tightly Coupled Memory with Nios II Tutorial describes the detailed instructions to create a Nios II system that uses tightly coupled memory.
- tcm.zip contains the C files required to run the design as explained in the document.
- Nios II Ethernet Standard Design Example provides the hardware platform on which the design runs.
The use of this design is governed by and subject to the terms and conditions of the Altera Hardware Reference Design License Agreement.
Figure 1. Nios II System with Tightly Coupled Instruction and Data Memory
- Nios II core with tightly coupled master
- On-chip memory
- DDRx SDRAM controller
- JTAG UART
- System timer
- High-resolution timer
- Performance counter
- LED parallel I/Os (PIOs)
System identification (ID) peripheral
For more information about using this example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.