Using Tightly Coupled Memory with Nios II Processor

This design example shows the use of tightly coupled memory in designs that include Nios® II processor. By enabling the processor’s tightly-coupled memory master, Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance critical applications. This design is provided for the following Altera® development kits:

  • Nios II Embedded Evaluation Kit, Cyclone® III Edition
  • Embedded Systems Development Kit, Cyclone III Edition
  • Stratix® IV GX FPGA Development Kit

Using This Design Example

The use of this design is governed by and subject to the terms and conditions of the Altera Hardware Reference Design License Agreement.

Figure 1. Nios II System with Tightly Coupled Instruction and Data Memory

Hardware Requirements

  • Nios II core with tightly coupled master
  • On-chip memory
  • DDRx SDRAM controller
  • JTAG UART
  • System timer
  • High-resolution timer
  • Performance counter
  • LED parallel I/Os (PIOs)
  • System identification (ID) peripheral

Related Links

For more information about using this example in your project, go to:

Nios II Software Developer’s Handbook (PDF)

Design Examples Disclaimer

These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.