Triple Speed Ethernet Design Example

This design example consists of both hardware and software. The hardware section consists of the Nios® II/f core with the reset vector pointing to the flash memory and exception vector pointing to the DDR3 memory. The hardware system also consists of the Triple Speed Ethernet MAC and a scatter-gather direct memory access core (PDF) for both TX and RX.

You can use the Triple Speed Ethernet design to evaluate the Triple Speed Ethernet media access control (MAC) or use it as a starting point for your own Ethernet system design. This design supports the following Altera® development kits:

Hardware Design Specifications

  • Nios II/f core with JTAG debug module
  • DDR3 SDRAM controller
  • Common flash interface (CFI) flash memory interface
  • Triple Speed Ethernet MAC
  • JTAG UART
  • System timer
  • High-resolution timer
  • Performance counter
  • LED parallel I/Os (PIOs)
  • Push-button PIOs
  • System ID peripheral
  • TX/RX SGDMA
  • On-chip memory

Using This Design Example

The use of this design is governed by and subject to the terms and conditions of the Altera Hardware Reference Design License Agreement.

Download the zip files suitable for your kit below.

Stratix IV:

Cyclone III:

Note: Cyclone III device family is not supported in ACDS version 14.0 and above.

Related Links

For more information you can also refer to the links below:

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.