This design example shows how to use the Vectored Interrupt Controller (VIC) with a Nios® II processor in a system design. The VIC provides a higher performance alternative to the default internal interrupt controller (IIC) of the Nios II processor.
The hardware design shows how to hook up a VIC with the Nios II processor. The software example shows how to use the Hardware Abstraction Layer (HAL)-enhanced interrupt application programming interface (API) to register an interrupt handler for a system based on the VIC component. The VIC can be daisy-chained as well if more than one VIC is required in the system.
Hardware Design Specifications
The hardware design used in this example targets the Cyclone® V SoC Development Kit. Key peripherals in this design includes:
- Nios II/f CPU core
- 16-KB on-chip RAM
- Interval timer
- Performance counter
- System timer
- JTAG UART
Using This Design Example
For information on how to run the design example, please refer to Vectored Interrupt Controller Core.
Download the files used in this example: vic_collateral_cv.zip.
The use of this design is governed by, and subject to, the terms and conditions of the Intel FPGA Hardware Reference Design License Agreement.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.