Remote System Upgrade over UART Based on Nios® II Processor with EPCQ

The design example implements basic remote configuration features in Nios® II-based systems with EPCQ for Cyclone® V E FPGA device. The UART interface is used to provide the remote configuration functionality. The UART terminal allows you to upload new FPGA designs for both user hardware and user software, at the same time you can also trigger reconfiguration from factory image to user image through the UART terminal.

 

Using This Design Example

This design runs on Cyclone® V E FPGA Development Kit. To run this example, download the Installation Package from Altera® Design Store. Follow instructions in the Reference Guide run the design.

 

Design Specifications

The design contains the following components:

  • Altera® PLL
  • Altera® Remote Update
  • Altera® Serial Flash Controller
  • JTAG UART
  • Nios® II Gen2 Processor
  • On-Chip Memory (RAM or ROM)
  • PIO (Parallel I/O)
  • Reset Controller
  • System ID Peripheral
  • UART (RS-232 Serial Port)

 

Block Diagram

 

Related Links

 

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