This design allows you to connect the RapidIO® Maintenance Master port to the System Maintenance Slave port for designs that don’t use the SOPC Builder flow and that don’t have a local host. In Serial RapidIO networks, this allows a remote processing endpoint to access the local Serial RapidIO capability registers
(CARs) and command and status registers (CSRs). The remote processing endpoint must initiate maintenance transactions to the local Altera® RapidIO core. The local RapidIO core processes the maintenance transactions by receiving them and routing them to the System Maintenance Slave port via the bridge. See Figure 1 for a high-level block diagram of the connectivity.
This bridge is written in Verilog HDL. It has been verified in register transfer level (RTL) functional simulations and has also been tested on hardware. Download the following Verilog HDL file, instantiate the bridge, and connect the instance according to the diagram.
Figure 1. Concept Block Diagram
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