Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature

The objective of this design example is to showcase the way to constraint the TSE_RGMII. This design example is only applicable when the delay feature (90 degree shift) of TX_CLK and RX_CLK of external PHY are turned on. It can run on 3 different speeds which are 10 MHz, 100 MHz, and 1000 MHz.

Assumption is made that the user is familiar with the Triple Speed Ethernet intellectual property (IP) Core, ALTDDIO, ALTPLL, TimeQuest and Static Timing Analysis, and double data rate (DDR) source synchronous concept.

How to Constraint

  1. Select the method of interface constraint: system centric method or FPGA centric method.
    • Different method requires different formula to calculate the delay value in the set_input_delay and set_output_delay command
    • This design example use system centric method
  2. Decide whether to turn on or turn off the delay feature (±90 degree shift) of external PHY as it will determine the type of alignment between the clock and data.
    • 90 degree shift -> center aligned
    • No shift -> edge aligned
    • This design example is applicable to delay feature of TX and RX of external PHY are turned on (90 degree shift) only
  3. Determine the desired launch and latch relationship.
    • There are 4 types of launch and latch relationship.They are Rise-Rise (RR), Rise-Fall (RF), Fall-Rise (FR) and Fall-Fall (FF) relationship
    • RGMII specification state that the LSB of data [3:0] will be sending out at the rising edge first and MSB of data [7:4] is sent out followed by the falling edge
    • The design of TSE with RGMII interface will capture the data at the rising edge first then followed by falling edge. It implies that the clock needs to be shifted +90 degree instead of -90 degree
    • Desired setup launch and latch relationship (Arrow in red): RR and FF
    • Desired hold launch and latch relationhip (Arrow in blue): FR and RF

    Figure 2. Lauch Clock and Latch Clock Relationship

  4. Constraint the RGMII Interface.The Synopsys Design Constraints (SDC) is based on the design and application.However, there are some main SDC needed for RGMII interface.

TX

  • create_clock
    • the clock that latch the data inside the FPGA prior to transmit to external PHY
  • create_generated_clock:
    • the clock with 90 degree phase shift that latch the data at the external PHY
  • set_false_path:
    • It is unwanted relationship not to be analyzed in timing analysis. In this design example, unwanted relationship for the setup is RF and FR while unwanted relationship for the hold is RR and FF
set_false_path -fall_from [data_clock] -rise_to [output_clock] -setup
set_false_path -rise_from [data_clock] -fall_to [output_clock] -setup
set_false_path -rise_from [data_clock] -rise_to [output_clock] -hold
set_false_path -fall_from [data_clock] -fall_to [output_clock] -hold
  • set_output_delay
set_output_delay -clock output_clock\
-max [expr $data_delay_max + $tsu - $clk_delay_min] \
[get_ports data_out] \
-add_delay

set_output_delay -clock output_clock\
-max [expr $data_delay_max + $tsu - $clk_delay_min] \
[get_ports data_out] \
-clock_fall \
-add_delay

set_output_delay -clock output_clock \
-min [expr $data_delay_min - $th - $clk_delay_max] \
[get_ports data_out ] \
-add_delay

set_output_delay -clock output_clock \
-min [expr $data_delay_min - $th - $clk_delay_max] \
[get_ports data_out ] \
-clock_fall \
-add_delay

TSE_RGMII RX

  • create_clock:
    • a virtual clock that latch the data inside the external PHY prior to transmit to the FPGA
  • create _clock:
    • the clock with 90 degree phase shift that latch the data inside the FPGA
  • set_false_path:
    • It is unwanted relationship not to be analyzed in timing analysis. In this design example, unwanted relationship for the setup is RF and FR while unwanted relationship for the hold is RR and FF
set_false_path -fall_from [data_clock] -rise_to [output_clock] -setup
set_false_path -rise_from [data_clock] -fall_to [output_clock] -setup
set_false_path -rise_from [data_clock] -rise_to [output_clock] -hold
set_false_path -fall_from [data_clock] -fall_to [output_clock] -hold

How to Verify

There are a few reports to checked in order to verify the source synchronous constraint is constrained properly

  1. Clock Report
    • Check on the 3 clock frequency (125 MHz , 25 MHz, and 2.5 MHz) and its phase
    • Core TX clock (FPGA): 125 MHz, 25 MHz, and 2.5 MHz
    • RGMII_TX_Clock (external PHY): 125 MHz +90º, 25 MHz +90º, and 2.5 MHz +90º
    • RGMII_RX_Clock (FPGA): 125 MHz +90º, 25 MHz +90º, and 2.5 MHz +90º
    • RGMII_RX_Virtual_Clock (external PHY) : 125 MHz, 25 MHz, and 2.5 MHz

  2. Clock Transfer Report
    • Check all the relationship on the setup and hold launch-latch relationship of RGMII interface for clock transfer
    • Desired Setup: RR and FF

    • Desired Hold: FR and RF

  3. All I/O Timing Report
    • Check if there is any failing path and launch-latch relationship according to the desired setup and hold launch-latch relationship
      • Input to register for setup and hold
      • Register to output for setup and hold

Notes:

  1. TSE_10_1_RGMII_SDC is the SDC file generated by Megafunction. It does not cover the RGMII SDC constraint. The RGMII SDC constraint is included in the RGMII SDC.
  2. Modfication in TSE_10_1_RGMII_SDC.sdc file:
    • Comment the derived_pll_clock (line 246) as it will prevent you from using create_gererated_clock command for the pll in RGMII.sdc
    • Change the name of FF_TX_CLK and FF_RX_CLK in line 59 and line 60 according to the design
  3. There are warnings which can be ignored during timing analysis. Please refer to the readme.txt found in TSE_RGMII_With_SDC.qar for details.
  4. Download the file used in this example: TSE_RGMII_With_SDC.qar

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

 

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