This design example shows the transceiver reset controller logic which controls the reset sequence of the Triple Speed Ethernet (TSE) transceiver as per recommended by the device handbook.
The document assumes that the user is familiar with the TSE intellectual property (IP) Core, the ALTGX megafunction and the transceiver architecture of the FPGA device.
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The transceiver reset controller, gx_rst_ctrl detects the gxb_pwrdn_in signal to power down the ALTGX transceiver using the gxb_powerdown signal. It also detects the pll_locked and rx_freqlocked signals to reset the ALTGX transceiver using the tx_digitalreset, rx_analogreset, and rx_digitalrest signals according to the reset sequence in the device handbook.
Figure 1 shows the simplified block diagram of the gx_rst_ctrl logic connect to the ALTGX transceiver.
gx_rst_ctrl connect to gx (rst_gx)
The state machine generates control signals like tx_digitalreset, rx_analogreset, and rx_digitalrest. As shown in Figure 2, the state machine has 7 states.
Figure 2. State Machine
The following section describes the states in the state machine in more detail.
stm_idle: This is the idle state. In this state, the counter, count_gxb_pwrdn is used to measure how long the gxb_pwrdn_in signal is asserted. When the gxb_pwrdn_in signal has been asserted for 1 µs, the idle state transits to the next state, the stm_gxb_pwrdn.
stm_gxb_pwrdn:This is the ALTGX transceiver's powerdown state. During this state, the gxb_powerdown output signal is asserted. When the gxb_pwrdn_in signal is deasserted, the state transits to the next, the stm_pll_locked.
stm_pll_locked: This is the state that detects the pll_locked signal. During this state, the gxb_powerdown output signal is deasserted. When the transceiver is locked, the pll_locked signal is asserted, and once it is detected, the state transits to the next, the stm_tx_digitalreset.
stm_tx_digitalreset: This is the transmitter's digital reset state. In this state, the tx_digitalreset output signal is deasserted. When the counter, count_rx_analogreset has counted two parallel clock cycles, the state transits to the next, the stm_rx_analogreset.
stm_rx_analogreset:This is the receiver's analog reset state. In this state, the rx_analogreset output signal is deasserted. When the receiver frequency is locked, the rx_freqlocked signal is asserted, and the state transits to the next, the stm_rx_freqlocked.
stm_rx_freqlocked:In this state, the counter, count_rx_digitalreset counts up till 4 µs, and then the state transits to the next, the stm_rx_digitalreset.
stm_rx_digitalreset: This is the receiver's digital reset state. In this state, the rx_digitalreset output signal is deasserted.
Points to note:
- Whenever the gxb_pwrdn_in signal is asserted for 1 µs, the state machine returns to the stm_gxb_pwrdnstate.
- Whenever the pll_locked signal is deasserted, the state machine returns to the stm_pll_lockedstate.
- Whenever the rx_freqlocked signal is deasserted, the state machine returns to the stm_rx_analogreset state.
For more information about instantiating TSE with an external ALTGX, please refer to the following design example:
- Triple Speed Ethernet (TSE) IP Core Resource Center
- Triple Speed Ethernet MegaCore Function User Guide (PDF)
- ALTLVDS Megafunction User Guide (PDF)
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