Mapping HPS IP Peripheral Signals to the FPGA Interface Design Example

AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface (PDF) introduces you to the design flow required to route a hard processor system (HPS) peripheral through the FPGA interface using Qsys and Quartus® Prime or Quartus II software. This application note includes a simple tutorial to demonstrate how to map HPS EMAC and I2C peripherals signals to the FPGA interface. It is based on the Golden Hardware Reference Design (GHRD) and provides step-by-step instruction on how to complete the mapping procedure.

The design is provided for the following Altera® development Kit:

Figure 1. Design Example Block diagram

Using This Design Example

To run this example, download the and unzip it to your hard drive. Then, follow the instructions in AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface (PDF).

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.