The Quartus® II software includes the classic timing analyzer that combines powerful features with ease-of-use.
For information on the classic timing analyzer, see the following resources:
For a brief overview of the classic timing analyzer, refer to the Quartus II Verification and Simulation product feature page.
To search for known classic timing analyzer issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Classic Timing Analyzer Resources
Table 1 provides links to available documentation on the classic timing analyzer.
Table 1. Classic Timing Analyzer Documentation
|Quartus II Classic Timing Analyzer(PDF)||This chapter of the Quartus II Development Software Handbook describes the features of the classic timing analyzer.|
|AN 411: Understanding PLL Timing for Stratix II Devices (PDF)||This application note describes how to analyze and constrain phase-locked loops (PLLs) using the classic timing analyzer.|
|Performing Equivalent timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace white paper (PDF)||This white paper shows how to perform equivalent static timing analysis between Altera's classic timing analyzer and Xilinx's Trace.|