The Quartus® Prime software incremental compilation feature is the most productive incremental design methodology for high-density FPGAs. It reduces compilation times by up to 70 percent while preserving the results of unchanged logic in your design.
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Incremental compilation resources
Table 1. Incremental Compilation Documentation
|Increasing Productivity with Quartus II Incremental Compilation (PDF)||This paper describes how an incremental compilation flow can improve your productivity when designing for high-density, high-performance FPGAs.|
|Design Planning with Quartus Prime Software||This handbook chapter discusses important FPGA design planning issues, provides recommendations, and describes various tools available for use with Altera FPGAs to help you improve design productivity. It briefly describes how planning can improve your success with incremental compilation.|
|Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design||
This handbook chapter describes Quartus Prime software features and design methodologies for incremental compilation, and includes various recommended design flows and application examples to help you meet your design goals. This is the primary document for details about incremental compilation.
|Best Practices for Incremental Compilation Partitions||This handbook chapter provides a set of guidelines to help you partition your design to take advantage of Quartus Prime incremental compilation, and to help you create a design floorplan (using Logic Lock Region) to support the flow.|
Table 2. Incremental Compilation Training and Demonstrations
|Incremental Compilation and Team-Based Design
You will see a demonstration of the incremental compilation feature used in both top-down (single Quartus II project) and bottom-up (multiple-project) team-based compilation methodologies.
This is a 10-minute online demonstration.
|Introduction to Incremental Compilation
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature. By the end of this training, you will be able to use Logic Lock Region in physical partitioning of your design. You will be able to segment your design into logical design partitions. You will be able to apply the incremental compilation methodology to both the top-down and bottom-up design flows.
This is a 2.5-hour online course.
|The Quartus II Software Design Series: Optimization
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and Logic Lock Region in the Quartus II software to reduce compilation times and preserve performance.
This is a 1-day instructor-led course.