Table 1 lists the IEEE Standard 1149.6-compliant boundary-scan description language (BSDL) files by Intel® FPGA device family. Intel FPGA device family supports IEEE std 1149.6 with the exception that SAMPLE instruction which is not supported for all HSSI pins. You can use these BSDL files for pre-configuration boundary-scan test (BST). For post-configuration, please use the Quartus® software to generate a post-configuration BSDL file. For the steps to generate BSDL files using the Quartus software, please refer to BSDL Files Generation in QII (DOC). You can use the BSDL file regardless of the device speed grade or temperature.