MAX+PLUS II Version 9.03 Update
System Requirements | Update Details | |
Support Notes | Legal Notice | |
Update Files | Installation Instructions |
Download
Download MAX+PLUS II Version 9.03 Update | |||
Operating System | Download | File Size | |
Windows NT, Windows 98, Windows 95
Installation Instructions | 903_pc.exe | 3.0 MB | |
UNIX Platform-Specific Files | |||
Download appropriate platform-specific
file(s)
Installation Instructions | Solaris 2.5+ | 903_solaris.tar.Z | 17.8 MB |
Sun OS 4.1.3+ | 903_sunos.tar.Z | 17.8 MB | |
HP-UX 10.2 | 903_hp.tar.Z | 19.9 MB | |
AIX 4.1 | 903_rs6000.tar.Z | 19.0 MB |
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System Requirements
Operating System | Windows NT, Windows 98, Windows 95
Solaris 2.5+ Sun OS 4.1.3+ HP-UX 10.2 AIX 4.1+ |
Software Version | MAX+PLUS® II 9.01, 9.02, 9.03 |
Software Update Details
This update can only be used with MAX+PLUS II version 9.01 or 9.02 for PCs or UNIX workstations. Do not use this update with any other version.
You should download and install this update (MAX+PLUS II version 9.03) if you wish to add the following support to MAX+PLUS II version 9.01 or 9.02.
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Programming and compilation support for EPM7064AE devices in 44-pin plastic J-lead chip carrier (PLCC), 44-pin thin quad flat pack (TQFP), and 100-pin TQFP packages
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Programming and compilation support for EPF10K50E devices in 144-pin, 208-pin, and 240-pin plastic quad flat pack (PQFP) packages
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Corrected synthesis of MAX+PLUS II VHDL designs for the following operations:
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Compare operations (>, >=, =, <, <=) on signals or ports of type
SIGNED
- Compare operations on integers that have negative values
MAX+PLUS II versions 9.01 and 9.02 treat these operations as
UNSIGNED
. This synthesis problem only impacts MAX+PLUS II VHDL designs. Third-party synthesis software tools (e.g., Exemplar Logic, Synopsys, and Synplicity) are not affected. -
Compare operations (>, >=, =, <, <=) on signals or ports of type
-
Corrected synthesis of VHDL designs when a bit or slice of a vector is assigned in a conditional statement and all branches of the conditional statement are not fully specified
- Corrected synthesis of Verilog HDL designs when using concatenation inside Case Statements
Software Update Files
The update contains the following files for PCs:
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The update contains the following common files for UNIX workstations:
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The update contains the following files for Solaris workstations:
- solaris/max2win
- solaris/maxplus2
The update contains the following files for HP-UX workstations:
- hp/max2win
- hp/maxplus2
The update contains the following files for RISC System 6000 workstations:
- rs6000/max2win
- rs6000/maxplus2
The update contains the following files for SunOS workstations:
- sunos/max2win
- sunos/maxplus2
Support
If you have a question or problem that is not answered by the information provided here or in MAX+PLUS® II. Help, please inquire in the mySupport web site.
Legal Notice
Altera's Software Subscription License Agreement governs installation and use of this software.