RapidIO IP Core Resource Center

Altera provides a range of complete FPGA solutions for the development of custom RapidIO® processing elements, bridges, and switches.

Altera Offers Two Distinct RapidIO MegaCore Functions

  • RapidIO II MegaCore® function complies with the RapidIO Specification Revision 2.2.
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE2 sequence - long control symbol
    • 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud lane rates with 1x, 2x, and 4x link widths
  • RapidIO MegaCore function complies with RapidIO Specification Revisions 1.3/2.1
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE1 sequence - short control symbol
    • 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1x and 4x link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO MegaCore function user guides.

The solutions, which include configurable RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:

Literature

Application Notes

Reference Designs

Altera Knowledge Database

The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding RapidIO.

See frequently viewed solutions:

Find additional solutions on the RapidIO MegaCore function.

Online Training Courses

Development Kits

The following development kits are available for the RapidIO MegaCore function: