ltera provides extensive documentation and support for the Triple-Speed Ethernet MegaCore® function to help you quickly and easily develop and debug Ethernet applications, such as line cards, NIC cards, and switches operating at 10/100 megabits per second (Mbps) for fast Ethernet or 1000 Mbps for Gbps Ethernet (GbE).
- Triple-Speed Ethernet MegaCore Function User Guide (PDF)
- MegaCore IP Library Release Notes and Errata (PDF)
- Archive of intellectual property (IP) release notes
- Archive of IP errata sheets
- AN440: Accelerating Nios® II Networking Applications (PDF)
- AN477: Designing RGMII Interfaces with FPGAs and HardCopy® ASICs (PDF)
- AN518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs (PDF)
- AN585: Simulation Debugging Using Triple Speed Ethernet Testbench (PDF)
- AN633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and
GX Transceiver (PDF)
- AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design (PDF)
AN633: Implementing Loopback in Triple-Speed Ethernet Designs with LVDS I/O and GX Transceiver
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
- Arria 10 GX: ACDS 15.0
- Arria V GX:
- Cyclone® V GX: ACDS 13.0 SP1 | ACDS 15.0
- Stratix V GX: ACDS 13.0 SP1 | ACDS 15.0
- Stratix IV GX: ACDS 13.0 SP1
- TSE: Constraint RGMII Interface of Triple-Speed Ethernet with the External PHY Delay Feature
- TSE: Instantiate TSE with External ALTGX / ALTLVDS
- TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver
- TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver
Altera Knowledge Database
The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding the Triple-Speed Ethernet MegaCore function.
See frequently viewed solutions:
- Can the Triple-Speed Ethernet rx_err and rx_err errors assert at the same time?
- Why does the Triple-Speed Ethernet standalone SGMII PCS with PMA exchange incorrect device ability status of 0x4001?
- Is PHY Loopback supported using the Triple-Speed Ethernet IP in Cyclone V or Arria V devices?
- Can Triple-Speed Ethernet MegaCore operate in 1000BASE-X unidirectional PCS mode?
- Why does the Triple-Speed Ethernet IP Core’s LED Link indicate that link is down after reset?
- ISS Fails on Designs Containing Triple-Speed Ethernet MAC or SG-DMA Components
Find additional solutions on the Triple-Speed Ethernet MegaCore function.
Online Training Courses
- 10/100/1000-megabytes (MB) Ethernet design with Altera transceiver devices
- Chinese version: 10/100/1000 MB Ethernet design with Stratix IV GX FPGAs
The following development kits are available for the Triple-Speed Ethernet MegaCore function: