Altera Software: Quartus Prime
Type: Answers
Area: Component


Last Modified: April 11, 2018

How do I enable Micron's MT25Q device support in replacement to End Of Life (EOL) EPCQ(>=256Mb) and EPCQ-L devices?

Description

As announced in PDN1802, EPCQ(>=256Mb) and EPCQ-L devices are being discontinued. The Micron* MT25Q devices can be use as replacement devices to support Active Serial configuration scheme in the Intel® Quartus® Prime software version 17.1 and later. To enable MT25Q support, add following variable into your quartus.ini file within the project directory:

pgm_allow_mt25q=on

If you do not have a quartus.ini file, use a text editor to create it, add the above variable and save this file as quartus.ini into your project directory or <Quartus Prime install directory>\bin64 (Windows) or <Quartus Prime install directory>/linux64 (Linux). When you open your project after adding the above variable, you should be able to see MT25Q devices in:

  • Convert Programming File tool
  • IPs accessing Active Serial Memory Interface (ASMI) port
  • Remote System Update IP

Since MT25Q devices are not listed in the Configuration Device setting under Configuration category of “Device and Pin Options” in the Quartus software, use the Convert Programming File tool to generate a programming file for Active Serial configuration with a MT25Q device.

In Quartus® Prime Standard edition version 17.1, the MT25Q devices are not listed in the Remote System Update IP. You can work around this by choosing an equivalent size of EPCQ or EPCQL device.

To enable MT25Q support in the standalone Quartus Prime Programmer, refer to the following steps:

  1. Place quartus.ini with the above variable into
    (a) the same directory where you will save a Programmer Object File (.pof) or a JTAG Indirect Configuration (.jic) file
    (b) <programmer install directory>\bin or bin64
  2. Start your standalone Quartus Prime programmer and open Convert Programming File tool from File menu. When you place the quartus.ini file in step 1(b), you can skip step 3 and 4.
  3. Specify the path and the name in the File name column of the Convert Programming File tool.
  4. Close the Convert Programming File tool and restart it.
  5. You should be able to see MT25Q devices in the Convert Programming File tool.

Additional Information : NVCR Programming

MT25Q devices have a non-volatile configuration register (NVCR).  The NVCR must be set to an appropriate value according to the MT25Q device and configuration mode in FPGA device families.  When using a JTAG Indirect Configuration (.jic) programming file or AS programming mode in the Quartus Prime software version 17.1 and later, the NVCR is automatically set during programming of the MT25Q device. If you are using a 3rd party programmer tool or your own solution, you must set the non-volatile configuration registers accordingly.

To set the non-volatile configuration register, follow these steps:

  1. Execute write enable operation:  opcode b’0000 0110
  2. Execute write non-volatile configuration register operation:  opcode b’1011 0001 followed by 16-bit register value

Set the 16-bit register value as b'1110 111y xxxx 1111 where y is the address byte (0 for 4-byte addressing and 1 for 3-byte addressing) and xxxx is the dummy clock value. When the xxxx value is from 0001 to 1110, the dummy clock value is from 1 to 14. When xxxx is 0000 or 1111, the dummy clock value is at the default value, which is 8 for standard fast read (ASx1) mode and 10 for extended quad input fast read (ASx4 mode).

Due to the register being non-volatile, you only have to set this register once as long as you do not change the configuration mode. Refer to the following tables for respective FPGA family device dummy clock value and the 16-bit NVCR register operation bits definition.

Table 1. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration Register Operation

FPGA Device

Address Bytes

Dummy Clock Cycles

ASx1

ASx4

• Pre 28nm Intel® FPGA (1)

• Intel® Cyclone® 10 LP

3-byte addressing

8

-

• Arria V

• Cyclone V

• Stratix V

3-byte addressing

12

12

4-byte addressing

4

10

• Intel® Arria 10

• Intel® Cyclone 10 GX

4-byte addressing

10

10

• Intel® Stratix® 10

3-byte addressing

-

10

 

Table 2. Non-Volatile Configuration Register Operation Bit Definition(5)

Bit

Description

Default Value

15:12

Number of dummy cycles. When this number is from 0001 to 1110, the dummy cycles is from 1 to 14.

0000 or 1111(2)(3)

11:5

Set these bits to 1111111.

1111111

4

Recommend setting this bit to 0 to disable RESET or HOLD function on DQ3 pin.(4)

1

3:1

Set these bits to 111.

111

0

Address byte setting.

• 0 = 4-byte addressing

• 1 = 3-byte addressing

1

Note 1:  Devices prior to V-series device family such as Arria II, Cyclone IV and Stratix IV.

Note 2: The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended dual input fast and standard fast read.

Note 3: For the Intel® Stratix® 10 device, use the default value 1111h to set 10 dummy clock cycles.

Note 4: Quartus Prime Programmer and active serial configuration don't use RESET or HOLD function.

Note 5: Non-volatile configuration register operation transfers the least significant byte (bit [7:0]) first, then transfers the most significant byte (bit[15:8]).

Workaround/Fix

Intel will support MT25Q devices in the Active Serial configuration scheme, the IPs accessing ASMI port and the Remote System Update IP without the above variable in the future version of Intel® Quartus® Prime software.