Article ID: 000076586 Content Type: Troubleshooting Last Reviewed: 05/23/2017

Extra gaps are inserted at RX in SerialLite III Continuous Mode

Environment

  • Intel® Quartus® Prime Pro Edition
  • Serial Lite III Streaming Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Extra gaps might be inserted in Standard Clocking Mode (SCM), when Source/TX sends data to RX continuously without any data-valid gap, the Sink/RX interface could still de-assert data-valid to the user logic.

    Resolution

    To work around this problem a buffering scheme could be implemented to store some words first before forwarding a received packet.

    This problem is scheduled to be fixed in a future release of the Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices