Due to a problem in Quartus Prime® software versions 16.1.2 and earlier, your Arria® 10 SerialLite™ III core might exhibit setup timing violations in the paths between "pld_10g_tx_pempty_reg node" and "altera standard synchronizer stdsync_txpempty|din_s1" of the type shown below:
From Node : seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:DUPLEX_WRAPPER.interlaken_inst|seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa:native_ilk_wrapper|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg
To Node : seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[5].stdsync_txpempty|din_s1
Launch Clock : seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[*]|tx_pma_clk
Latch Clock : seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[0]|tx_pma_clk
To work around this problem, the user must modify the generated ip .sdc file (seriallite_iii_streaming*.sdc).
The original .sdc contraints found below:
set_max_skew -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex|stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.85
set_net_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85
set_max_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] 100
set_min_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -100
Should be replaced with the following contraints:
set inst_xcvr_list [get_entity_instances twentynm_xcvr_native]
foreach each_xcvr_inst \$inst_xcvr_list {
if { [string equal "quartus_sta" \$::TimeQuestInfo(nameofexecutable)] } {
set_max_skew -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.85
}
set_net_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85
set_max_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] 100
set_min_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -100
}
This problem has been fixed starting in software version 17.0 of the Quartus Prime® software.