Critical Issue
In some configurations of the RapidIO® II IP core, generated VHDL simulation will encounter compilation error where a port is missing in the entity instantiating another entity.
Example Error in ModelSim® simulator.
Port "<port_name>" of entity "<entity name>" is not in the component being instantiated.
This error is only found in variations where the I/O Master, I/O Slave, Doorbell, Maintenance or Pass-through modules are disabled.
Verilog version is not impacted.
Use Verilog version of the simulation testbench.