How do you perform pre- or post-compilation VHDL simulation in Model Technology V-System/VHDL?

Description For pre-compilation simulation, perform the following steps. 1. Create your design in the MAX PLUS II software. 2. Create a new directory in your local working directory. 3. Copy your design <file name>.vhd into the new directory. 4. Before compiling the <file name>.vhd< file, create a design library to hold the compilation results by typing the following command at a UNIX or PC prompt. A subdirectory will be created in your current working directory. vlib <name directory> 5. Compile your <file name>.vhd file by typing the following command: vcom <file name>.vhd 6. Invoke the simulator, by typing the following command: vsim For post-compilation simulation, create a design in MAX PLUS II, compile it, and then use the resulting VHDL Output File (.vho) to complete steps 2 through 6.