Hardware and software simulation results differ when using preadder mode with an unsigned signal

This simulation issue was found in the Quartus II software release version 13.0, but impacts versions 11.1 through 13.0. When you directly instantiate digital signal processing (DSP) or media access control (MAC) WYSIWYG in your design, your hardware and software simulation results will differ when using preadder mode with an unsigned signal. The simulation results differ when preadder subtraction and unsigned preadder input are used at the same time; on the hardware, the preadder input is sign extended, so all input to multiplier is treated as signed. This issue applies to the Arria V and Cyclone V devices.

The 13.1 Quartus II software release includes legality checks to prevent you from producing this error. There is no workaround for previous versions.