Article ID: 000079703 Content Type: Troubleshooting Last Reviewed: 10/31/2013

Conflicting Pin Assignment Error with UART0

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If your HPS design was created with Qsys v13.0 or earlier, and you open it in v13.0 SP1 or later, you might see an error message similar to the following:

    The selected peripheral UART0 and <component name> are conflicting.

    In v13.0 and earlier, the HPS soft IP component for the Arria V SoC HPS has incorrect pin set definitions. The UART0 pin assignments in HPS I/O Set 0 and HPS I/O Set 2 are interchanged. When you open a design created with the incorrect pin set definitions, the swapped pin locations overlap with other component pins.

    Resolution

    To work around this issue, perform the following steps:

    1. Open your SoC HPS design in Qsys.
    2. Edit the HPS component.
    3. Open the Peripheral Pin Multiplexing page.
    4. Change UART0 pin multiplexing from HPS I/O Set 0 to HPS I/O Set 2, or vice-versa.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs