Article ID: 000086992 Content Type: Troubleshooting Last Reviewed: 04/19/2017

RapidIO MegaCore Function User Guide Testbench Instructions for ModelSim Require Modification

Environment

  • Intel® Quartus® Prime Pro Edition
  • RapidIO (IDLE1 up to 5.0 Gbaud) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The RapidIO MegaCore Function User Guide includes instructions to run the demonstration testbench and simulate in the Mentor Graphics ModelSim simulator. To simulate this testbench correctly in the ModelSim simulator, you must use the command ld-debug to ensure that relevant information is not compiled away by the simulator. However, those instructions erroneously specify you should use the command ld.

    If you implement the instructions in the user guide without modifying the ld command, ModelSim simulation might fail and display the error message "Optimization failed. Error loading design".

    Resolution

    To work around this issue, replace the ld command with the ld-debug command in the instructions the user guide provides to simulate the testbench in the ModelSim simulator.

    This issue is fixed in version 17.0 of the RapidIO IP Core User Guide.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices