Article ID: 000075987 Content Type: Troubleshooting Last Reviewed: 11/14/2014

Incorrect SerialLite II SDC File Generated for Altera 28-nm Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When the SerialLite II IP core generates the SDC file, you must edit the file to include the transceiver clockout information in accordance to your design. The SerialLite II IP core generates the SDC file independently.

    The transceiver clock name for the Custom PHY IP core’s tx_clkout and rx_clkout must be used in the asynchronous clock group constraint in the SDC file to integrate your design between the SerialLite II IP core and the Custom PHY IP core.

    The transceiver clock name for the Custom PHY IP core’s tx_clkout and rx_clkout must also be set asynchronously to the core clock (rdp/hdp clock) in the SDC file before you compile and run the timing analyzer.

    This issue affects all SerialLite II designs using Arria V, Cyclone V, or Stratix V devices.

    This issue will not be fixed.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices