Description
When you generate the JESD204B design example with L=8 configuration, during Quartus compilation of the design example, you will encounter the following critical warning:
Critical Warning (18234): ATX PLLs < module name 1 > and < module name 2 > are < 0 > ATX PLLs apart. ATX PLLs with VCO frequencies within 100 MHz of each other must be separated by < 3 > or more ATX PLLs. The < 3 > or more intervening ATX PLLs can be operated at different VCO frequencies. Modify the ATX PLLs location constraints in the Assignment Editor to make ATX PLLs at least < 3 > ATX PLLS apart.
Resolution
To continue to use the transceivers in non-bonded mode, reassign the serial data pins in non-consecutive banks that will meet the minimum spacing requirements of the ATX PLL. For bonded mode, use a single ATX PLL in xN bonded configuration to clock the transceiver channels in two banks.
This issue will be fixed in a future release.