Critical Issue
The link parameter (rx_lane_count
) signal clock in the DisplayPort
design crosses to undesired clock domain. This issue may not cause any functional
failure because the signal is handled correctly after sycnhronization. However, this
issue may cause timing violation on the (rx_lane_count
) signal
path.
You may ignore this timing violation.
This issue is fixed in version 15.1 Update 1 of the DisplayPort IP core.