Article ID: 000081271 Content Type: Troubleshooting Last Reviewed: 07/18/2016

DisplayPort Timing Violation on the Link Parameter Signal

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The link parameter (rx_lane_count) signal clock in the DisplayPort design crosses to undesired clock domain. This issue may not cause any functional failure because the signal is handled correctly after sycnhronization. However, this issue may cause timing violation on the (rx_lane_count) signal path.

    Resolution

    You may ignore this timing violation.

    This issue is fixed in version 15.1 Update 1 of the DisplayPort IP core.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices