Article ID: 000078685 Content Type: Troubleshooting Last Reviewed: 11/18/2017

Spectra-Q Timing Analyzer Might Apply TimeQuest Deration Incorrectly to Designs with the set_timing_derate Assignments Targeting Blocks with Minimum Period or Pulse Width Limits

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    For Arria® 10 and Cyclone® 10 designs, If you apply the set_timing_derate Tcl command to blocks with minimum period or minimum pulse width limits, Spectra-Q TimeQuest might apply the timing deration to your design incorrectly.

    This issue affects the Quartus® Prime Standard Edition software and the Quartus Prime Pro Edition software.

    Resolution

    Run Spectra-Q Timing Analyzer with the force_dat option:

    • Run quartus_sta -force_dat from the command line.
    • Run create_timing_netlist -force_dat from the Spectra-Q TimeQuest GUI.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA
    Intel® Cyclone® 10 FPGAs