Critical Issue
The Transaction Layer Configuration Space Signals data
(tl_cfg*)
driven by the Hard IP for PCI Express are incorrectly sampled
in the FPGA fabric. Consequently, a setup or hold time violation may occur. The
Quartus Prime software does not report the violation because this multi-cycle path
is not constrained. If a timing violation occurs, the system may hang.
This problem is fixed in version 16.0.1 or later of the Quartus Prime software.