Article ID: 000076977 Content Type: Troubleshooting Last Reviewed: 12/05/2016

Traffic generator in SerialLite III Streaming IP core design example causes lane sequence error when using burst length of 1.

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Lane sequence error occurs when burst length is set to 1 in the Traffic Generator module in SerialLite III Streaming IP core hardware testing design example. This impact Stratix V, Arria V GZ, Arria 10, and Stratix 10 devices.

    Resolution

    This issue has no workaround. This issue will be fixed in future releases.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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