Critical Issue
If you place an ALTLVDS_RX megafunction or an ALTLVDS_TX megafunction on the left edge or the right edge of a Cyclone V device, compilation might fail with an error similar to the following:
Error (175020): Illegal constraint of pin to the region
(89, 4) to (89, 16): no valid locations in region
This error occurs because, by default, the PLL in the ALTLVDS megafunction is instantiated in LVDS compensation mode. LVDS Compensation mode is not supported on the left or right edges of Cyclone V devices.
To prevent the error, perform one of the following:
- If you want to generate an ALTLVDS_RX megafunction or an ALTLVDS_TX megafunction with Use external PLL turned off:
for an ALTLVDS_RX megafunction, add the following Quartus II assignment to your project Quartus Settings File (.qsf):
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT
-to <ALTLVDS instance>|ALTLVDS_RX_component|auto_generated|pll_sclk
for an ALTLVDS_TX megafunction, add the following Quartus II assignment to your project .qsf:
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT
-to <ALTLVDS instance>|ALTLVDS_TX_component|auto_generated|pll_fclk
- If you want to generate an ALTLVDS_RX megafunction or an ALTLVDS_TX megafunction with Use external PLL turned on, ensure that, when you configure the Altera_PLL megafunction, you set its Operation Mode to direct.
Note: After you perform either of the above workarounds, during compilation the Quartus II software might generate a warning similar to the following:
Critical Warning (11141): PLL "my_pll:my_pll_inst|my_pll_0002:my_pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"
drives a non-DPA LVDS interface, but the PLL is not in LVDS compensation
mode.
You may safely ignore this warning if:
- you place the ALTLVDS megafunction on the left edge or the right edge of the Cyclone V device AND
- the Operation Mode of the PLL is set to direct.