Article ID: 000085093 Content Type: Troubleshooting Last Reviewed: 02/16/2015

When does the Parallel Flash Loader (PFL) IP assert the flash_nreset signal?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The flash_nreset signal will be asserted in any of the following cases:

(1) The device with the PFL design is powered up or configured.
(2) The pfl_nreset input signal is asserted.
(3) When Quartus® II programmer is used to program the flash memory, if the PFL has programming mode enabled.

If you want to assert flash_nreset, reset the PFL using pfl_nreset. 

Related Products

This article applies to 12 products

Stratix® V FPGAs
Stratix® IV FPGAs
Stratix® III FPGAs
Intel® MAX® 10 FPGAs
MAX® V CPLDs
MAX® II CPLDs
Cyclone® V FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® III FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Arria® II FPGAs

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