Article ID: 000080931 Content Type: Troubleshooting Last Reviewed: 04/17/2013

Why does the Qsys interconnect block the next AXI transaction until a previous one completes ?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a restriction in the Qsys Interconnect in the Quartus® II Software version 12.1sp1 and earlier only supports in-order transactions.  

    To maintain in-order transaction the Qsys interconnect will block pending transactions to different slaves by varifying the transaction addresses and de-asserting the ready signal until the current transaction completes.

    Resolution

    To reduce transaction blocking, consolidate transactions to the same slave.  If a Master sends transactions to the same slave the Qsys interconnect will accept the  next transaction by asserting ready signal before the previous transaction completes, providing the slave can also accept next transaction.

    This restriction is currently scheduled to be addressed in a future release of the Quartus II Software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices