Description
Due to a problem in the Quartus® II software version 12.1, you may see this error during generation of Qsys systems that utilize IRQ Clock Crosser Logic.
Resolution
To workaround this problem follow the steps below:
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Open the altera_irq_clock_crosser_hw.tcl file located in the Quartus II installation directory in a text editor:
<Quartus II install directory>\ip\altera\merlin\altera_irq_clock_crosser -
Remove the line: "set_module_property SIMULATION_MODEL_IN_VERILOG true"
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Add the line: "add_file altera_irq_clock_crosser.sv {SYNTHESIS SIMULATION}"
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Save the file and re-generate the Qsys system
This problem is fixed for the Quartus II software version 13.0 and later.