Device Family: Stratix V E, Stratix V GS, Stratix V GT, Stratix V GX
Type: Answers
Area: EMIF, Intellectual Property


Last Modified: November 28, 2016
Version Found: v12.1 Service Pack 1
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller

Description

You may see timing violation when you disable DQS tracking in DDR3 controller following the steps in this KDB solution:
http://www.altera.com/support/kdb/solutions/rd01062012_793.html

The timing violation happens when the controller is named with the string “controller“.   

Workaround/Fix

The workaround for this issue is by changing the “controller” to “alt*controller” in <instance>_p0_report_timing_core.tcl

Change:

if { ! } {
       
set controller_regs [get_registers |*controller_*inst|*]
       
set inst_other_if
   
} else {

       
set controller_regs [get_registers |*:*controller_*inst|*]
       
set inst_other_if
   
}

 


To:

if { ! } {
       
set controller_regs [get_registers | *alt*controller_*inst|*]
       
set inst_other_if
   
} else {

       
set controller_regs [get_registers |*:* alt*controller _*inst|*]
       
set inst_other_if
   
}

This issue will be fixed in a future release of Quartus® II software.