This error occurs when you compile the MAX® II Development Kit USB Reference Design (versions earlier than 6.0.1) with the Quartus® II software versions 5.0 and later.
This error is due to a restriction introduced in the Quartus II sofware version 5.0 to make the software comply more closely with the Verilog HDL standard. Input ports cannot be of type reg, but this is not enforced in Quartus II software versions 4.2 and earlier.
To avoid these errors, delete the line "reg [10:0] bus;" and other similar lines where input types are declared as reg.
This problem is fixed beginning with the MAX II Development Kit version 6.0.1. Use mySupport to request the latest version. You can also download version 6.0.1 of the MAX II Development Kit from the following link: ftp.altera.com/outgoing/devkit/MII_1270N_Kit-v6.0.1.exe.