The number of instructions which take more than one clock cycle is determined by the complexity of the ALU and its pipelining architecture. Therefore, the minimum and maximum cycles per instruction depends on the core you choose (Nios® II/f, Nios II/s, Nios II/e).
The Nios II/f core has a larger, more complex ALU which executes some instructions faster. The Nios II/e core has a smaller ALU which in general takes more clock cycles to execute instructions, trading logic utilization for performance. For example, using the Nios II/f core, the barrel shift instruction would be performed by first swapping words before shifting individual bits, allowing the barrel shift instruction to complete in fewer clock cycles. The Nios II/e core simply shifts one bit at a time through a 32 bit word, which could take up to 32 clock cycles.
For details on each Nios II core including the cycles per instruction, refer to chapter 5, Nios II Core Implementation Details, in the Nios II Processor Reference Handbook (http://www.altera.com/literature/lit-nio2.jsp).