Solution ID: rd03142001_6451
Last Modified: February 13, 2006
Product Category: N/A
Product Area: N/A
Product Sub-area: N/A


To instantiate a VHDL module inside a Verilog design, make sure the two files are in the same directory and that they have been added to the project for compilation. Next, simply instantiate the lower level VHDL design by name in the Verilog file.

The following is an example of a top-level Verilog file called top_ver.v that instantiates a lower-level VHDL file called bottom_vhdl.vhd:

module top_ver (p, q, out);
input    q, p;
output   out;
bottom_vhdl u1 (.a(q), .b(p), .c(out));

VHDL file (bottom_vhdl.vhd)

USE ieee.std_logic_1164.ALL;

ENTITY bottom_vhdl IS
PORT (a, b : IN std_logic;
      c : OUT std_logic);
END bottom_vhdl;

ARCHITECTURE a OF bottom_vhdl IS
   Process (a, b)
       c <= a and b;
END process;


Note that this is supported by direct synthesis in the Quartus II software. This may or not be supported in other EDA tools. Please check with the tool vendor for details.

Workaround / Fix