Article ID: 000084312 Content Type: Troubleshooting Last Reviewed: 08/07/2023

Why is DSP Block merging not occuring?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Quartus® II software may not merge independent multipliers into one or two DSP Blocks when using the Cyclone® V, Arria® V, and Stratix® V device families.  

 

For example:

Three 9x9 independent multipliers are fit into three DSP Blocks instead of merged into one DSP Block.

Two 16x16 independent multipliers are fit into two DSP Blocks instead of merged into one DSP Block.

Three 18x18 independent multipliers are fit into three DSP Block instead of merged into two DSP Block.

 

Resolution

The merging of independent multipliers will automatically take effect when Quartus® II software has determined insufficient DSP Blocks on the device or within a LogicLock region.  

Related Products

This article applies to 15 products

Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.